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8k/16kx18 deep sync fifos fax id: 5413 cy7c4255 CY7C4265 preliminary cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 july 1995 C revised november 1996 1cy 7 c42 65 features ? high-speed, low-power, first-in first-out (fifo) memories ? 8k x 18 (cy7c4255) ? 16k x 18 (CY7C4265) ? 0.5 micron cmos for optimum speed/power ? high-speed 100-mhz operation (10 ns read/write cycle times) ? low power i cc =45 ma ? fully asynchronous and simultaneous read and write operation ? empty, full, half full, and programmable almost empty and almost full status flags ? ttl compatible ? retransmit function ? output enable (oe ) pins ? independent read and write enable pins ? center power and gr ound pins for reduced noise ? supports free-running 50% duty cycle clock inputs ? width expansion capability ? depth expansion capability ? 64-pin plcc and 64-pin tqfp ? pin-compatible density upgrade to cy7c42x5 family ? pin-compatible density upgrade to idt72205/15/25/35/45 functional description the cy7c4255/65 are high-speed, low-power, fi rst-in first-out (fifo) memories with clo cked read and write interfaces. all are 18 bits wide and are pin/functionally compatible to the cy7c42x5 synchronous fifo family. the cy7c4255/65 can be cascaded to increase fifo d epth. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and commu- nications buffering. these fifos have 18-bit input and output ports that are con- trolled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and a write enable pin (wen ). when wen is asserted, data is written into the fifo on the rising edge of the wclk signal. while wen is held active, data is continu- ally written into the fifo on each cycle. the output port is controlled in a similar manner by a free-running read clock (rclk) and a read enable pin (ren ). in addition, the cy7 c4255/65 have an output enable pin (oe ). the read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 100 mhz are achievable. retransmit and synchronous almost full/almost empty flag features are available on these devices. depth expansion is pos sible using the cascade input (wxi , rxi ), cascade output (wxo , rxo ), and first load (fl ) pins. the wxo and rxo pins are connected to the wxi and rxi pins of the next device, and the wxo and rxo pins of the last device should be connected to the wxi and rxi pins of the first device. the fl pin of the first device is tied to v ss and the fl pin of all the remaining devic- es should be tied to v cc . q 0C 17 4255C1 threeCstate output register read control flag logic write control write pointer read pointer reset logic expansion logic input register flag program register d 0C 17 ren rclk ff ef pae wen wclk rs fl /rt wxi oe ram array 8k x 18 16k x 18 paf wxo /hf rxi rxo smode logic block diagram
cy7c4255 CY7C4265 2 preliminary functional description (continued) the cy7c4255/65 provides five status pins. these pins are decod- ed to determine one of five states: empty, almost empty, half full, almost full, and full (see table 2 ). the half full flag shares the wxo pin. this flag is valid in the stand-alone and width-expansion configurations. in the depth expansion, this pin provides the expansion out (wxo ) information that is used to signal the next fifo when it will be activated. the empty and full flags are synchronous, i.e., they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty states, the flag is updated exclusively by the rclk. the flag denoting full states is updated exclusively by wclk. the synchronous flag archi- tecture guarantees that the flags will remain valid from one clock cycle to the next. the almost empty/almost full flags become synchronous if the vcc/smode is tied to vss. all configurations are fabricated using an advanced 0.5 m cmos technology. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings. pin configurations 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 top view 60 59 58 57 56 55 54 53 52 51 50 49 48 3132 33 34 35 36 37 38 3940 4142 43 5 4 3 2 1 68 66 65 64 63 62 61 q 14 q 13 gnd q 12 q 11 v cc q 10 q 9 gnd q 8 q 7 v cc d 14 d 13 d 12 d 11 d 10 d 9 v cc d 8 gnd d 7 d 6 d 5 d 4 2728 2930 98 7 6 47 46 45 44 q 6 q 5 gnd q 4 d 3 d 2 d 1 d 0 25 26 v cc /smode tqfp top view 4255C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 16 plcc d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 q 14 q 13 gnd q 12 q 11 v cc q 10 q 9 gnd q 8 q 7 q 6 q 5 gnd q 4 v cc 4255C3 cy7c4255 CY7C4265 cy7c4255 CY7C4265 selection guide 7c4255/65C10 7c4255/65C15 7c4255/65C25 7c4255/65C35 maximum frequency (mhz) 100 66.7 40 28.6 maximum access time (ns) 8 10 15 20 minimum cycle time (ns) 10 15 25 35 minimum data or enable set-up (ns) 3 4 6 7 minimum data or enable hold (ns) 0.5 1 1 2 maximum flag delay (ns) 8 10 15 20 active power supply current (i cc1 ) (ma) commercial 45 45 45 45 industrial 50 50 50 50 cy7c4255 CY7C4265 density 8k x 18 16k x 18 package 64-pin plcc,tqfp 64-pin plcc,tqfp
cy7c4255 CY7C4265 3 preliminary pin definitions signal name description i/o function d 0 C17 data inputs i data inputs for an 18-bit bus q 0C17 data outputs o data outputs for an 18-bit bus wen write en able i enables the wclk input ren read enable i enables the rclk input wclk write clock i the rising edge clocks data into the fifo when wen is low and the fifo is not full. when ld is asserted, wclk writes data into the programmable flag-offset register. rclk read clock i the rising edge clocks data out of the fifo when ren is low and the fifo is not empty. when ld is asserted, rclk reads data out of the programmable flag-off- set register. wxo /hf write ex pansion out/half full flag o dual-mode pin: single device or width expansion C half full status flag. cascaded C write expansion out signal, c onnected to wxi of next device. ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk. ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk. pae programmable almost empty o when pae is low, the fifo is almost empty based on the almost-empty offset value programmed into the fifo. pae is asynchronous when v cc /smode is tied to v cc ; it is synchronized to rclk when v cc /smode is tied to v ss . paf programmable almost full o when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo. paf is asynchronous when v cc /smode is tied to v cc ; it is synchronized to wclk when v cc /smode is tied to v ss . ld load i when ld is low, d 0 C 17 (q 0 C 17 ) are written (read) into (from) the programma- ble-flag-offset register. fl /rt first load/ retransmit i dual-mode pin: cascaded C the fi rst device in the daisy chain will have fl tied to v ss ; all other devices will have fl tied to v cc . in standard mode or width expansion, fl is tied to v ss on all devices. not cascaded C t ied to v ss . retransmit function is also available in stand-alone mode by strobing rt. wxi write ex pansion input i cascaded C conn ected to wxo of previous device. not cascaded C tied to v ss . rxi read expansion input i cascaded C conn ected to rxo of previous device. not cascaded C tied to v ss . rxo read expansion output o cascaded C conn ected to rxi of next device. rs reset i resets device to empty condition. a reset is required before an init ial read or write operation after power-up. oe output enable i when oe is low, the fifos data outputs drive the bus to which they are con- nected. if oe is high, the fifos outputs are in high z (high-impedance) state. v cc /smode synchronous almost empty/ almost full flags i dual-mode pin asynchronous almost empty/almost full flags C tied to v cc . synchronous almost empty/almost full flags C tied to v ss . (almost empty synchronized to rclk, almost full synchronized to wclk.)
cy7c4255 CY7C4265 4 preliminary maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................C65 c to +150 c ambient temperature with power applied............................................C55 c to +125 c supply voltage to ground potential ............... C0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... C0.5v to +7.0v dc input voltage ........................................... - 0.5v to v cc +0.5v output current into outputs (low)............................. 20 ma static discharge voltage ........................................... >2001v (per milCstdC883, method 3015) latch-up current ..................................................... >200 ma notes: 1. t a is the instant on case temperature. 2. see the last page of this specification for group a subgroup testing information. 3. the v ih and v il specifications apply for all inputs except wxi , rxi . the wxi , rxi pin is not a ttl input. it is connected to either rxo , wxo of the previous device or v ss . 4. the v ih and v il specifications apply for all inputs except wxi , rxi . the wxi , rxi pin is not a ttl input. it is connected to either rxo , wxo of the previous device or v ss. 5. input signals swi tch from 0v to 3v with a rise/ fall time of less than 3 ns, clocks and clock enables switch at 20mhz, while data i nputs switch at 10mhz. outputs are unl oaded. icc1(typical) = (25ma+(freq-20mhz)*(1.0ma/mhz)) 6. all inputs = v cc C 0.2v, except rclk and wclk (which are switching at frequency = 20 mhz), and fl /rt which is at v ss . all outputs are unloaded. 7. tested initially and after any design changes that may affect these parameters. 8. tested initially and after any process changes that may affect these parameters. operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial [1] C40 c to +85 c 5v 10% electrical characteristics over the operating range [2] 7c42x5C10 7c42x5C15 7c42x5C25 7c42x5C 35 parameter description test conditions min. max. min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih [3] input high voltage 2.0 v cc 2.0 v cc 2.0 v cc 2.0 v cc v v il [4] input low voltage C0.5 0.8 C0.5 0.8 C0.5 0.8 C0.5 0.8 v i ix input leakage current v cc = max. C10 +10 C10 +10 C10 +10 C10 +10 m a i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc C10 +10 C10 +10 C10 +10 C10 +10 m a i cc1 [5] active power supply current coml 45 45 45 45 ma ind 50 50 50 50 ma i cc2 [6] average standby current coml 10 10 10 10 ma ind 15 15 15 15 ma capacitance [7,8] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 5 pf c out output capacitance 7 pf
cy7c4255 CY7C4265 5 preliminary ac test loads and waveforms [9, 10] 3.0v 5v output r1 1.1k w r2 680 w c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 1.91v equivalent to: th venin equivalent 4255C4 410 w all input pulses 4255C5 switching characteristics over the operating range 7c42x5C10 7c42x5C15 7c42x5C25 7c42x5C35 parameter description min. max. min. max. min. max. min. max. unit t s clock cycle frequency 100 66.7 40 28.6 mhz t a data access time 2 8 2 10 2 15 2 20 ns t clk clock cycle time 10 15 25 35 ns t clkh clock high time 4.5 6 10 14 ns t clkl clock low time 4.5 6 10 14 ns t ds data set-up time 3 4 6 7 ns t dh data hold time 0.5 1 1 2 ns t ens enable set-up time 3 4 6 7 ns t enh enable hold time 0.5 1 1 2 ns t rs reset pulse width [11] 10 15 25 35 ns t rsr reset recovery time 8 10 15 20 ns t rsf reset to flag and output time 10 15 25 35 ns t prt retransmit pulse width 30 35 45 55 ns t rtr retransmit recovery time 60 65 75 85 ns t olz output enable to output in low z [12] 0 0 0 0 ns t oe output enable to output valid 3 7 3 8 3 12 3 15 ns t ohz output enable to output in high z [12] 3 7 3 8 3 12 3 15 ns t wff write clock to full flag 8 10 15 20 ns t ref read clock to empty flag 8 10 15 20 ns t pafasynch clock to programmable almost-full flag [13] (asynchron ous mode, v cc /smode tied to v cc ) 12 16 20 25 ns t pafsynch clock to programmable almost-full flag (synchronous mode, v cc /smode tied to v ss ) 8 10 15 20 ns t paeasynch clock to programmable almost-empty flag [13] (asynchronous mode, v cc /smode tied to v cc ) 12 16 20 25 ns notes: 9. c l = 30 pf for all ac parameters except for t ohz . 10. c l = 5 pf for t ohz . 11. pulse widths less than minimum values are not allowed. 12. values guaranteed by design, not currently tested. 13. t pafasynch , t paeasynch , after program register write will not be valid until 5 ns + t paf (e ) .
cy7c4255 CY7C4265 6 preliminary t paesynch clock to programmable almost-full flag (synchronous mode, v cc /smode tied to v ss ) 8 10 15 20 ns t hf clock to hal f-full flag 12 16 20 25 ns t xo clock to expansion out 6 10 15 20 ns t xi expansion in pulse width 4.5 6.5 10 14 ns t xis expansion in set-up time 4 5 10 15 ns t skew1 skew time between read clock and write clock for full flag 5 6 10 12 ns t skew2 skew time between read clock and write clock for empty flag 5 6 10 12 ns t skew3 skew time between read clock and write clock for programmable almost empty and pro- grammable almost full flags (synchronous mode only) 10 15 18 20 ns switching characteristics over the operating range (continued) 7c42x5C10 7c42x5C15 7c42x5C25 7c42x5C35 parameter description min. max. min. max. min. max. min. max. unit
cy7c4255 CY7C4265 7 preliminary switching waveforms notes: 14. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 15. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. it the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk rising edge. write cycle timing t clkh t clkl no operation t ds t skew1 t ens wen t clk t dh t wff t wff t enh wclk d 0 Cd 17 ff ren rclk 4255C6 [14] read cycle timing t clkh t clkl no operation t skew2 wen t clk t ohz t ref t ref rclk q 0 Cq 17 ef ren wclk oe t oe t ens t olz t a t enh valid data 4255C7 [15]
cy7c4255 CY7C4265 8 preliminary notes: 16. the clocks (rclk, wclk) can be free-ru nning during reset. 17. after reset, the outputs will be low if oe = 0 and three-state if oe = 1. 18. when t skew2 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew2 < minimum specification, t frl (maximum) = either 2*t clk + t skew2 or t clk + t skew2 . the latency timing applies only at the empty boundary (ef = low). 19. the first word is avai lable the cycle after ef goes high, always. switching waveforms (continued) reset timing t rs t rsr q 0C q 17 rs t rsf t rsf t rsf oe =1 oe =0 ren , wen, ld ef ,pae ff ,paf , hf 4255C8 [16] [17] d 0 (firstvalid write) first data word latency after reset with simultaneous read and write t skew2 wen wclk q 0 Cq 17 ef ren oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 Cd 17 4255C9 t a [18] [19]
cy7c4255 CY7C4265 9 preliminary switching waveforms (continued) d1 d0 t ens t skew2 empty flag timing wen wclk q 0 Cq 17 ef ren oe t ds t enh rclk t ref t a t frl d 0 Cd 17 d0 t skew2 t frl t ref t ds t ens t enh 4255C10 t ref [18] [18] next data read data write no write data in output register full flag timing ff wclk q 0 Cq 17 ren oe rclk t a d 0 Cd 17 data read t skew1 t ds t ens t enh wen t wff t a t skew1 t ens t enh t wff data write no write t wff low 4255C11 [14] [14]
cy7c4255 CY7C4265 10 preliminary notes: 20. pae is offset = n. number of data words into fifo already = n. switching waveforms (continued) t enh halfCfull flag timing wen wclk hf ren rclk t clkh t hf t ens half full + 1 or more t clkl t ens half full or less half fullor less t hf 4255C12 t enh programmable almost empty flag timing wen wclk pae [20] ren rclk t clkh t pae t ens n + 1 words in fifo t clkl t ens t pae n words in fifo 4255C13
cy7c4255 CY7C4265 11 preliminary notes: 21. pae offset - n. 22. t skew3 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than t skew3 , then pae may not change state until the next rclk. 23. if a read is preformed on this rising edge of the read clock, there will be empty + (n - 1) words in the fifo when pae goes low. 24. paf offset = m. number of data words written into fifo already = 8192 - (m + 1) for the cy7c4255 and 16384 - (m + 1) for the CY7C4265. 25. paf is offset = m. 26. 8192 - m words in cy7c4255 and 16384 - m words in CY7C4265. 27. 8192 - (m + 1) words in cy7c4255 and 16384 - (m + 1) CY7C4265. switching waveforms (continued) note t enh programmable almost empty flag timing (applies only in smode (smode is low)) wclk pae rclk t clkh t ens t clkl t ens t pae synch n + 1 words infifo 4255C14 t enh t ens t enh t ens t pae synch ren wen wen2 t skew3 note [22] 21 23 note t enh programmable almost full flag timing wen wclk paf [25] ren rclk t clkh t paf t ens t clkl t ens t paf 4255C15 fullC m words infifo fullC (m+1) words in fifo [27] [26] 24
cy7c4255 CY7C4265 12 preliminary notes: 28. if a write is performed on this rising edge of the write clock, there will be full - (m - 1) words of the fifo when paf goes low. 29. paf offset = m. 30. t skew3 is the minimum time between a rising rclk and a rising wclk edge for paf to change state during that clock cycle. if the time between the edge of rclk and the rising edge of wclk is less than t skew3 , then paf may not change state until the next wclk rising edge. switching waveforms (continued) note note t enh programmable almost full flag timing (applies only in smode (smode is low)) wclk paf rclk t clkh t ens fullC m words in fifo t clkl t ens fullC m + 1 words in fifo 4255C16 t enh t ens t enh t ens t paf ren wen wen2 t skew3 t paf synch 28 29 [26] [30] t enh write programmable registers ld wclk t clkh t ens t clkl pae offset d 0 Cd 17 wen t ens paf offset pae offset t clk d 0 C d 11 t ds t dh 4255C17
cy7c4255 CY7C4265 13 preliminary notes: 31. write to last physical location. 32. read from last physical location. switching waveforms (continued) t enh read programmable registers ld rclk t clkh t ens t clkl pae offset q 0 Cq 17 wen t ens paf offset pae offset t clk unknown t a 4255C18 write expansion out timing wen wclk wxo t clkh t ens t xo t xo 4255C19 note 31 note 31 read expansion out timing ren wclk rxo t clkh t ens t xo t xo 4255C20 note 32 write expansion in timing wclk wxi t xi t xis 4255C21
cy7c4255 CY7C4265 14 preliminary notes: 33. clocks are free run ning in this case. 34. the flags may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at t rtr . 35. for the synchronous pae and paf flags (smode), an appropriate clock cycle is necessary after t rtr to update these flags. switching waveforms (continued) read expansion in timing rclk rxi t xi t xis 4255C22 retransmit timing ren /wen fl /rt t prt t rtr 4255C23 ef /ff and all async flags hf /pae /paf [33, 34, 35]
cy7c4255 CY7C4265 15 preliminary architecture the cy7c4256/65 consists of an array of 8k/16k words of 18 bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren , wen , rs ), and flags (ef , pae , hf , paf , ff ). the cy7c4255/65 also includes the control signals wxi , rxi , wxo , rxo for depth expansion. resetting the fifo upon power-up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition signified by ef being low. all data outputs go low after the falling edge of rs only if oe is asserted. in order for the fifo to reset to its default state, a falling edge must occur on rs and the user must not read or write while rs is low. fifo operation when the wen signal is active (low), data present on the d 0C17 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren signal is active low, data in the fifo mem- ory will be presented on the q 0 C 17 outputs. new data will be pre- sented on each rising edge of rclk while ren is active low and oe is low. ren must set up t ens before rclk for it to be a valid read function. wen must occur tens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0 C 17 outputs when oe is deasserted. when oe is enabled (low), data in the output register will be available to the q 0 C 17 outputs after t oe . if devices are cascaded, the oe function will only output data on the fifo that is read enabled. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and under flow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0 C 17 outputs even after additional reads occur. programming the cy7c4255/65 devices contain two 14-bit offset registers. data present on d 0C13 during a program write will determine the distance from empty (full) that the almost empty (almost full) flags become active. if the user elects not to program the fifos flags, the default offset values are used (see table 2 ). when the load ld pin is set low and wen is set low, data on the inputs d 0 C 13 is written into the empty offset register on the first low-to-high transition of the write clock (wclk). when the ld pin and wen are held low then data is written into the full offset register on the second low-to-high transition of the write clock (wclk). the third transi- tion of the write clock (wclk) again writes to the empty offset register (see ta bl e 1 ). writing all offset registers does not have to occur at one time. one or two offset registers can be written and then, by bring- ing the ld pin high, the fifo is returned to normal read/write oper- ation. when the ld pin is set low, and wen is low, the next offset register in sequence is written. the contents of the offset registers can be read on the output lines when the ld pin is set low and ren is set low; then, data can be read on the low-to-high transition of the read clock (rclk). flag operation the cy7c4255/65 devices provide five flag pins to indicate the condition of the fifo contents. empty and full are syn- chronous. pae and paf are synchronous if v cc /smode is tied to v ss . full flag the full flag (ff ) will go low when device is full. write operations are inhibited whenever ff is low regardless of the state of wen . ff is synchronized to wclk, i.e., it is exclusively updated by each rising edge of wclk. empty flag the empty flag (ef ) will go low when the device is empty. read operations are inhibited whenever ef is low, regardless of the state of ren . ef is synchronized to rclk, i.e., it is exclusively updated by each rising edge of rclk. programmable almost empty/almost full flag the cy7c4255/65 features programmable almost empty and almost full flags. each flag can be programmed (described in the programming section) a specific distance from the cor- responding boundary flags (empty or full). when the fifo contains the number of words or fewer for which the flags have been programmed, the paf or pae will be asserted, signifying that the fifo is either almost full or almost empty. see table 2 for a description of programmable flags. when the smode pin is tied low, the paf flag signal transition is caused by the rising edge of the write clock and the pae flag transition is caused by the rising edge of the read clock. table 1. write offset register. ld wen wclk [36] selection 0 0 writing to offset registers: empty offset full offset 0 1 no operation 1 0 write into fifo 1 1 no operation
cy7c4255 CY7C4265 16 preliminary retransmit the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if ne cessary. the retransmit (rt) input is active in the stand-alone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred and at least one word has been read since the last rs cycle. a high pulse on rt resets the inter- nal read pointer to the first physical location of the fifo. wclk and rclk may be free running but must be disabled during and t rtr after the retransmit pulse. with every valid read cycle after retransmit, previously accessed data is read and the read pointer is incriminated until it is equal to the write pointer. flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data written to the fifo after activation of rt are transmitted also. the full depth of the fifo can be repeatedly retransmitted. table 2. flag truth table. number of words in fifo ff paf hf pae ef 7c4255 C 8k x 18 7c4265 C 16k x 18 0 0 h h h l l 1 to n [37] 1 to n [37] h h h l h (n+1) to 4096 (n+1) to 8192 h h h h h 4097 to (8192C(m+1)) 8193 to (16384 C( m+1)) h h l h h (8192Cm) [38] to 8191 (16384Cm) [38] to 16383 h l l h h 8192 16384 l l l h h notes: 36. the same selection sequence applies to reading from the registers. ren is enabled and read is performed on the low-to-high transition of rclk. 37. n = empty offset (default values: cy7c4255/CY7C4265 n = 127). 38. m = full offset (default values: cy7c4255/CY7C4265 n = 127).
cy7c4255 CY7C4265 17 preliminary width expansion configuration the cy7c4255/65 can be expanded in width to provide word widths greater than 18 in increments of 18. during width ex- pansion mode all control line inputs are common and all f lags are available. empty (full) flags should be created by anding the empty (full) flags of every fifo; the pae and paf flags can be detected from any one device. this technique will avoid reading data from, or writing data to the fifo that is stag- gered by one clock cycle due to the variations in skew be- tween rclk and wclk. figure 1 demonstrates a 36-word width by using two cy7c4255/65s. figure 1. block diagram of 8k x18/16k x 18synchronous fifo memory used in a width expansion configuration. 4255C24 ff ff ef ef write clock (wclk) write enable (wen ) load (ld ) programmable(pae ) half full flag (hf ) full flag (ff ) 7c4255 7c4265 18 36 data in (d) reset (rs) 18 reset (rs) read clock (rclk) read enable (ren ) output enable (oe ) programmable (paf ) empty flag (ef ) 18 data out (q) 18 36 first load (fl ) write expansion in (wxi ) read expansion in (rxi ) 7c4255 7c4265
cy7c4255 CY7C4265 18 preliminary depth expansion configuration (with programmable flags) the cy7c4255/65 can easily be adapted to applications re- quiring more than 8192/16384 words of buffering. figure 2 shows depth expansion using three cy7c42x5s. maximum depth is limited only by signal loading. follow these steps: 1. the first device must be designated by grounding the first load (fl ) control input. 2. all other devices must have fl in the high state. 3. the write expansion out (wxo ) pin of each device must be tied to the write expansion in (wxi ) pin of the next device. 4. the read expansion out (rxo ) pin of each device must be tied to the read expansion in (rxi ) pin of the next device. 5. all load (ld ) pins are tied together. 6. the half-full flag (hf ) is not available in the depth expansion configuration. 7. ef , ff , pae , and paf are created with composite flags by oring together these respective flags for monitoring. the composite pae and paf flags are not precise. figure 2. block diagram of 8kx18/16kx18 synchronous fifo memory with programmable flags used in depth expansion configuration. 4255C25 writeclock (wclk) writeenable (wen ) reset (rs ) load (ld ) ff paf paf ff ef pae pae ef wxi rxi first load (fl ) read clock (rclk) read enable (ren ) outputenable (oe ) wxo rxo paf ff ef pae wxi rxi wxo rxo v cc fl paf ff ef pae wxi rxi wxo rxo 7c4255 7c4265 v cc fl datain (d) data out (q) 7c4255 7c4265 7c4255 7c4265
cy7c4255 CY7C4265 19 preliminary document #: 38-00468-a ordering information 8kx18 deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4255C10ac a65 64-lead thin quad flatpack commercial cy7c4255C10jc j81 68-lead plastic leaded chip carrier cy7c4255C10ai a65 64-lead thin quad flatpack industrial cy7c4255C10ji j81 68-lead plastic leaded chip carrier 15 cy7c4255C15ac a65 64-lead thin quad flatpack commercial cy7c4255C15jc j81 68-lead plastic leaded chip carrier cy7c4255C15ai a65 64-lead thin quad flatpack industrial cy7c4255C15ji j81 68-lead plastic leaded chip carrier 25 cy7c4255C25ac a65 64-lead thin quad flatpack commercial cy7c4255C25jc j81 68-lead plastic leaded chip carrier cy7c4255C25ai a65 64-lead thin quad flatpack industrial cy7c4255C25ji j81 68-lead plastic leaded chip carrier 35 cy7c4255C35ac a65 64-lead thin quad flatpack commercial cy7c4255C35jc j81 68-lead plastic leaded chip carrier cy7c4255C35ai a65 64-lead thin quad flatpack industrial cy7c4255C35ji j81 68-lead plastic leaded chip carrier 16kx18 deep sync fifo speed (ns) ordering code package name package type operating range 10 CY7C4265C10ac a65 64-lead thin quad flatpack commercial CY7C4265C10jc j81 68-lead plastic leaded chip carrier CY7C4265C10ai a65 64-lead thin quad flatpack industrial CY7C4265C10ji j81 68-lead plastic leaded chip carrier 15 CY7C4265C15ac a65 64-lead thin quad flatpack commercial CY7C4265C15jc j81 68-lead plastic leaded chip carrier CY7C4265C15ai a65 64-lead thin quad flatpack industrial CY7C4265C15ji j81 68-lead plastic leaded chip carrier 25 CY7C4265C25ac a65 64-lead thin quad flatpack commercial CY7C4265C25jc j81 68-lead plastic leaded chip carrier CY7C4265C25ai a65 64-lead thin quad flatpack industrial CY7C4265C25ji j81 68-lead plastic leaded chip carrier 35 CY7C4265C35ac a65 64-lead thin quad flatpack commercial CY7C4265C35jc j81 68-lead plastic leaded chip carrier CY7C4265C35ai a65 64-lead thin quad flatpack industrial CY7C4265C35ji j81 68-lead plastic leaded chip carrier
cy7c4255 CY7C4265 preliminary ? cypress s emiconduc tor corporation, 1996. the information contained herein is subject to change without noti ce. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. package diagrams 64-lead thin plastic quad flat pack a65 68-lead plastic le aded chip carrier j81

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